A DRAM cell consists of a transistor with a drain-source passage connected between a bit line and a cell node and a storage capacitor connected between the above mentioned cell node and a cell plate. Accordingly, as the density of memory cells are increased, DRAM cells having three-dimensional capacitors with trench and stack structures have been developed in order to maximize the capacitances of the storage capacitors within the limited area of the DRAM cells. A trench type storage capacitor is formed in a groove of a semiconductor substrate, while a stacked type storage capacitor is formed upon a semiconductor substrate.
The trench capacitor type DRAM cells are advantageous because they permit topological flattening and sufficient capacitance in a high density DRAM. But they are weak in protecting against .alpha. particles due to soft errors, and have further problems such as punch-through and leakage between the trenches. On the other hand, the stacked capacitor type DRAM cells are relatively simple in their manufacturing process and provide strong protection against soft errors because of their small diffusion areas. But they do however have drawbacks such as significant topological differences due to the fact that the capacitors are stacked upon the transistors.
FIG. 1 is a vertical section view of a convention stacked capacitor type DRAM cell. This type of DRAM cell will be briefly described below.
A P type well 2 is formed upon a P type substrate 1. A field oxide layer 4 is formed to isolate or separate the memory cells of the DRAM. A P.sup.+ channel stopper layer 3 is formed under the field oxide layer 4. Thereafter, a gate oxide layer 5 is formed, and upon this gate oxide layer 5, an N.sup.+ impurity doped polycrystalline silicon layer 6 is formed which serves as the gate electrode of a switching transistor. At the same time, another polycrystalline silicon layer 7 is formed which serves as the gate electrode of a memory cell which is disposed adjacent to the field oxide layer 4.
Next the N.sup.+ drain region 9 and N.sup.+ source region 8 of the switching transistor are formed. Then, an insulating layer 10 for electrically insulating the polycrystalline layers 6, 7, and a polycrystalline layer 11 used as a storage node, are formed. A selected portion of the source region 8 is exposed. Thereafter, an N.sup.+ doped thin polycrystalline silicon layer 12 which serves as an electrode of the capacitor is formed so that it contacts the exposed portion of the source region 8. Then, a dielectric layer 13 of the storage capacitor is formed upon the surface of the thin polycrystalline silicon layer 12. Another N.sup.+ doped polycrystalline silicon layer 14 which serves as another electrode of the storage capacitor is formed.
An insulating layer 15 and a flattening layer 16 are formed upon the polycrystalline silicon layer 14. A conductive layer 17 contacting the drain region 9 and which serves as a bit line is formed upon the flattening layer 16.
The above structure is described in Pages 600 through 603 of IEDM (International Electron Devices Meeting), 1988, under the heading "Stacked Capacitor Cells for High-density Dynamic RAMs".
The above described conventional stacked capacitor cell makes it possible to obtain sufficient capacitance from the limited occupation area of the memory cell. However, due to the thickness of the polycrystalline silicon layer which is used as an electrode of the capacitor, the topological variation of the device diminishes the workability of subsequent process steps.